Polymorphic programmable units employing plural levels of phased sub-instruction sets

ABSTRACT

This disclosure relates to a programmable unit employing plural levels of sub-instruction sets in addition to conventional instruction sets. The conventional level of instruction sets is employed to specify computational routines and other processing algorithms to be carried out by the unit. Each instruction in a conventional set is implemented in the unit by a sequence of first level sub-instructions which specify the various operations to be carried out within the unit which operations are comprised within the specific routine. In turn, the various first level sub-instructions are implemented by second level sub-instructions which specify the various control signals required to set the various gates as required for the particular unit operation to be carried out. With this hierarchy of sub-instruction sets, first level sub-instruction sets may be interchanged dynamically during the operation of the unit to dynamically change the processing capability of the unit. This eliminates the requirement for any special logic circuitry to accommodate particular computational routines and allows the arithmetic logic unit to be designed as multiples of the basic logic unit in accordance with particular desired data path widths. A manner is disclosed by which the interchanging of first level sub-instruction sets provides for placing the unit in different control modes such as input-output control or processing control. A manner is also disclosed by which interchanging of different first level sub-instruction sets accommodates the execution of programs written in different program language forms.

This is a division of application Ser. No. 825,569, filed May 19, 1969.

BACKGROUND OF THE INVENTION

This invention relates to a programmable unit adapted to performdifferent tasks such as computation and other data processing functionsand also input-output control. More specifically, this invention relatesto such a programmable unit employing plural levels of sub-instructionsets.

Computer usage has expanded to such a large extent that there is now amarket for a complete spectrum of computers for performing a greatvariety of computational tasks and other data processing applications.At one time, the so-called large computer system was thought of as beingadapted primarily for complex mathomatical routines and the small dataprocessing systems were thought mathematical as being adapted primarilyfor business and accounting routines involving rather simple arithmeticoperations being performed on a large batch of data. In more recentyears, business applications have become of such a magnitude as torequire large size data processing systems, and, conversely,applications have been found for medium and small size data processingsystems to handle scientific applications as well as data logging. Thereis, therefore, a need for a variety of computer processing systemsranging from the very small to the very large each of which can handlenot only business and scientific applications but also control of datatransmission, data acquisition and the like.

As a greater variety of computer applications were found, differentsystems were individually tailored for those applications. For thosesituations in which large scale computational problems were involved,requiring many hundreds or thousands of iterative steps, emphasis wasplaced both on speed of execution and on the number of data bits thatcould be handled in a given cycle of instruction execution. For such asituation, the system was designed to handle large data widths and alsomany of the algorithmic processes required to be performed upon thatdata were implemented directly in wired circuitry to achieve greaterspeed of instruction execution. It was mainly because of theseconsiderations that the large scale or scientific computer was soexpensive. Where the market demanded a more inexpensive computer, such acomputer system was designed with the cost factor in mind, as a resultof which the circuits and systems involved were relatively simple andthe various algorithms were implemented by the programmer. As a result,the time of execution of the program was relatively slow not onlybecause the system had to carry out each individual stop of the program,but also, because the system was designed to handle data of relativelysmall widths to conserve the circuitry of the system. Since the designerof both types of systems would have to design and manufacture twodifferent arithmetic-logic units for the separate systems, he would losethe economic advantage that would be found with volume production of butone type of design.

The above disadvantage is also inherent in computer systems which are ofsufficient size as to require the control of input-output operationsconcurrently with control of computational and other logic operations.Such separate I-O control units may resemble and, sometimes even are,general purpose digital computers in their own right, complete with anarithmetic unit and sometimes even a local storage. However, thefunction and, therefore, the design of the I-O control unit still isdifferent from that of the general purpose computer with which it isassociated.

Another disadvantage associated with systems of different designs isthat of programming incompatibility between the different systems. Sincesome routeins were implemented in circuitry in larger size systems, onlyone instruction was required to be executed in order to perform thatroutine. On the other hand, in a smaller system, a plurality of suchinstructions would have to be implemented to carry out the same routine.This lack of program compatibility was even more acute between systemsbuilt by different companies since different designers employeddifferent instruction formats which varied in length and also employeddifferent field sizes within the instruction format. To overcome suchdifferences in the "machine languages", a variety of differentprogramming languages were developed among the more common of which areFortran, Cobal and Algol. Programs written in such programming languagescould be encoded and used in different computer systems; however, suchprograms had to first be translated into the machine language of aparticular system which translation performed by an executive programsometimes called a compiler, and, if such an executive program had notbeen provided for a particular programming language, then the computeruser would have to rewrite his program in a language for which thesystem did have a compiler.

Various types of systems architecture have been devised to minimize boththe circuit or hardware incompatibility and also the programming orsoftware incompatibility described above. While minimization hasoccurred within particular product lines, attempts to minimizeincompatibility between various programming languages has really onlyled to the creation of even more programming languages. Particulararchitectural techniques which have been employed in the prior artinclude the design of modular processing units and storage units whereinthe capability of the system can be increased by adding additionalprocessing units and the storage capacity of the system can be increasedby adding storage units. Other techniques include the design of datapath widths of different members of a product line to be multiples ofsome basic unit segment and adapting the instruction format for theproduct line also to be multiples of that basic segment.

A particular architectural concept that allowed for more flexibility incomputer design and also in computer programming has been the concept ofmicroprograms or microinstructions. Initially, a microinstruction wasmerely a set of control bits employed within a macroinstruction format.Such control bits were employed to provide corrective measures duringthe execution of a multiply instruction or shift instruction and thelike. This concept then evolved to where the macroinstruction specifiedthe particular routine to be performed, such as the addition of twooperands, and the execution of the macroinstructions was through asequence of executions of microinstructions each of which specified theparticular gates to be set at the different sequence times. Since aplurality of macroinstructions could be implemented by a finite set ofmicroinstructions, it was recognized that these same microinstructionscould be stored in a separate storage to be addressed in any particularsequence upon the execution of different macroinstructions. It wasfurther recognized that various sequences of microinstructions could beformulated to carry out particular operations and separately stored inany memory. Thus, a great variety of sequences of microinstructionscould be created to carry out a great variety of routines, and, when agiven computer system was designed to perform particular routines, onlythose required sequences of microinstructions could be stored to becalled forth for execution upon the execution of specific individualmacroinstructions.

The concept of microinstruction or microprograms, then, became one ofsub-instructional sets which were masked or hidden from the programmerthus simplifying the writing of particular programs by minimizing thenumber of individual specific steps that had to be called for by theprogrammer. The concept of microprogramming allowed the computerdesigner to design a more inexpensive computer system that could providea great variety of routines to the computer user without the requirementof individual functions being implemented in hard-wired circuitry.

While this concept of sequences of microinstructions or sequences ofsub-instructions served to provide the programmer with greater ease ofprogram formulation, and also served to provide the computer designerwith a greater flexibility and variety of options in meeting therequirements of particular systems architectural design, the obtainmentof circuit compatibility between various member systems of a productline and the obtainment of program compatibility both between variousprogramming languages and between the machine languages of the varioussystems have not yet been provided by the prior art.

OBJECTS OF THE INVENTION

It is, then, an object of the present invention to provide an improvedprogrammable unit the functional capabilities of which may bedynamically changed during the operation of the unit.

It is another object of the present invention to provide an improvedprogrammable unit which may be dynamically changed during its operationto execute programs written in different program languages.

It is still another object of the present invention to provide animproved programmable unit that may be dynamically changed during itsoperation to execute sequences of computational instructions or toexecute sequences of control instructions for input-output datatransfers.

It is still another object of the present invention to provide animproved programmable unit that may be dynamically changed from acomputational mode to an input-output control mode without therequirement of separate circuitry for each mode.

It is still another object of the present invention to provide animproved programmable unit a plurality of which may be employed in acomputation array to provide different computational and data handlingoperations without any special adaptation being provided to any unit ofthat array.

It is still a further object of the present invention to provide animproved programmable unit having an expandable number of functionallogic units to perform a variety of logic operations under the controlof sub-instruction sets.

It is still a futher object of the present invention to provide animproved programmable unit having an architectural design that may beemployed in a variety of such units having different computationalcapacities and capabilities.

SUMMARY OF THE INVENTION

The flexibility provided by microprogramming, that is, the employment ofa single level of sub-instruction sets still is not sufficient toachieve the above objects of the present invention. In order toaccomplish the above-stated objects, the present invention employs notonly a first level of sub-instruction sets which are hereinafter calledM instructions but also employs a second level of sub-instruction sets,which are phased, hereinafter called N instructions. Themacroinstructions or systems instructions shall be called Sinstructions. In one sense, the implementation of the phased Ninstructions may be thought of as a decoder for the M instructions whichare encoded rather than being merely control signals. The phased Ninstructions may be just appropriate combinations of a particularrequired control signals or may also be encoded signals. Thus, theimplementation of a phased second level of sub-instruction sets or Ninstruction sets provides an additional order of flexibility over thatprovided by the microprogramming techniques of the prior art.

Since the system of the present invention can perform all algorithmsunder the control of plural levels of instruction sets, special circuitsneed not be provided for specific algorithms but only to provide thebasic Boolean connectives. Thus, the present invention adapts itself tothe employment of multiple identical logic units arranged in parallelfashion which multiple is changable from one computer system to anotherhaving a different data path width without any modification of the basiclogic unit. This is made possible because of the versatitity achieved bythe present invention whereby different algorithms can be implemented bydifferent strings of M instructions, and, thus, the N instructionsdefining the control signals can be independent of the type of algorithmrequired to be carried out.

Additionally, the present invention encompasses an array of programmableunits individually programmed and identical in form and circuitry eachof said units being dynamically changable by changing M instruction setsto operate in a data processing mode or in an input-output control mode.

A feature, then, of the present invention resides in a programmablesystem and methods with which the system operates wherein provision ismade for the storage of different sequences of instructions selectedfrom a first level of sub-instruction sets with the provision furtherbeing made for the decoding or implementation of such first levelsub-instructions by instructions selected from a second level ofsub-instruction sets, the particular sequences of first levelsub-instructions being selected or addressed in accordance with theinformation content of an instruction selected from the higher level setof instructions. A specific feature of the present invention resides inmeans to address and select the particular second level sub-instructionsin an overlapped or phased manner to accommodate the execution ofconditional first level sub-instructions during a particular timeperiod.

A particular feature of the present invention resides in a programmableunit and method for operating this unit wherein separate sequences offirst level sub-instructions are employed to control the operation ofthe unit in different modes such as a processing mode and aninput-output control mode which sequences can be addressed and selectedin accordance with specific higher level instructions.

Another particular feature of the present invention resides in aprogrammable unit and a method for operating that unit whereinparticular different sequences of first level sub-instructions areprovided for the execution of higher level instructions expressed indifferent program language forms which specific sequences of first levelsub-instructions can be selected according to the particular languageform of the set of the higher level instructions.

Another particular feature of the present invention resides in aprogrammable unit having arithmetic and logic circuitry formed of aplurality of modular logic units which modular units are activated underthe control of two levels of sub-instructions.

DESCRIPTION OF THE DRAWINGS

The above and other objects and advantages and features of the presentinvention will become more readily apparent from a review of thefollowing specification when taken in conjunction with the drawingswherein:

FIG. 1A is a representation of a programmable unit of the presentinvention;

FIG. 1B is a representation of an array of programmable units of thepresent invention;

FIG. 2 is a diagrammatic representation of the control portion and thearithmetic logic unit of the present invention;

FIG. 3 is a detailed representation of the arithmetic logic unit of thepresent invention;

FIG. 4 is an alternative representation of the arithmetic logic unit;

FIGS. 5-11 are schematic diagrams of various logic circuitry of thepresent invention;

FIG. 12 is a schematic diagram of the memory interface;

FIGS. 13-16 are representations of the formats of various instructionsemployed in the present invention;

FIG. 17 is a schematic diagram of the second level sub-instructiondecoder;

FIG. 18 is a schematic diagram of the first level sub-instructiondecoder;

FIG. 19 is a table of N control signals of the Phase 2 and 3 controlfields of the N instruction;

FIG. 20 is a table of N control signals of the Phase 3 control field ofthe N instruction;

FIGS. 21-23 are sets of timing diagrams illustrating instructionexecution overlap; and

FIGS. 24 and 25 illustrate M instruction sequences that can be employedin the present invention.

GENERAL DESCRIPTION OF THE SYSTEM Definitions

Certain terms are used frequently throughout the following specificationand it will be understood that these terms are to be interpreted inaccordance with the following definitions.

Program language form is any format which may be encoded into binarysignals which format may be employed by a programmer or computer userwithout any knowledge of the circuitry in a specific processing system.

S instruction is an instruction containing information specifying aroutine or a process to be carried out on data sets. An S instruction iscomparable to a macroinstruction or machine language instruction ofprior art.

M instruction is an instruction containing information specifying aoperation to be carried out in a processing system where one or moresuch operations are required to carry out a process called for by the Sinstruction. An M instruction is comparable to a microinstructionemployed in the prior art.

N instruction is an instruction containing information specifyingparticular control signals which are to be employed within theprocessing system to activate the implementation of an M instruction.One or more N instructions may be required to implement an Minstruction.

Prior art concepts of microprogramming provided two basic advantages.First, the programmer is relieved of having to specify the individualsteps required to accomplish a given operation which steps are specifiedby the string of microinstructions called for by the macroinstruction.Secondly, the computer designer is relieved of the requirement ofspecial circuitry to perform each special function to be provided by thesystem. Furthermore, the designed system an perform a greater number ofcomputational operations with a given instruction format since theoperation code of the instruction format is no longer required tospecify the particular machine operations.

The present invention employs three separate systems as one singlesystem: namely the S system, the M system and the N system. Each systemin turn employs its own memory and its own instruction decoder. Theroster of N instructions is normally fixed but may be adapted to bealternable. The roster of M instructions can be changed dynamicallyalterable. the normal operation of the system. Each unique set of Minstructions defines a particular interpretation capability for aparticular set of S instructions. Each S instruction may specify acomplete algorithm the steps of which are defined by a string of Minstructions. The S instruction is the equivalent of themacroinstruction or machine language instruction of the prior art.However, no particular set of S instructions is inherently required bythe present invention and, thus, a plurality of different sets of Sinstructions can be employed including sets of S instructions writtenaccording to different programming languages. Furthermore, the set ofcommands to control input-output data transfer is implemented in thepresent invention by a particular set of S instructions. Each set of Sinstructions is interpreted in the system of the present invention by arespective separate set of M instructions each of which is in turnimplemented by the roster of N instructions.

The manner in which the present invention is implemented will be betterunderstood from a review of the drawings. Referring first to FIG. 1A,there is illustrated therein the basic arrangement of a programmableunit of the present invention. The programmable unit is formed of twobasic sections, namely an arithmetic logic unit or ALU and a controlsection. Memory 20 is illustrated as being divided into three sections,namely, main memory 20A, microprogram memory 20B and N memory 20C. Mainmemory 20A will be of the normal destructive readout or DRO type memorynormally employed in data processing systems as the storage unit. MPmemory 20B is normally of the non-destructive readout type or NDRO typememory. N memory 20C is preferably one of the NDRO type but may be aread only memory type or ROM. All three memories may be of the magneticthin film type or solid state memory; however, N memory 20C inherentlywill be chosen to be of the type having the fastest memory cycle. Thesystem of FIG. 1A is completed by a plurality of input-output devices 9which are coupled to main memory 20A by a switching unit 8 under thecontrol of programmable unit 10.

Before a detailed description of programmable unit 10 is given, aparticular application of such a programmable unit will be described inreference to FIG. 1B to illustrate the versatility of the presentinvention. In FIG. 1B, a plurality of processor units 11 . . . , 14 areconnected in an array through switch interlock 13 which also connects tomemory units 21, 22 and 23, as well as to a plurality of input-outputdevices 9 which are coupled to the array of switching units 8. Suchinput-output dovices may include magnetic tape transports of the typedisclosed in Rayfield et al, U.S. Pat. No. 3,185,365, or such devicesmay include paper tape readers such as disclosed in Baird et al, U.S.Pat. No. 3,069,078. The respective processor units 11 . . . , 14 are ofthe type illustrated as processor unit 10 in FIG. 1A and are adapted tobe placed in different modes in accordance with the present invention.Thus, as illustrated in the table accompanying FIG. 1B, units 11 and 12may be placed in an input-output control mode during a particular tasktime while units 13 and 14 would operate in a process mode. At a latertask time when no input-output operations are required, all four unitswould be placed in a process mode. At a still later task time whenfurther input-output operations are required, one of the units in thearray such as unit 13 would be placed in an input-output control mode.The purpose of the table accompanying FIG. 1B is merely to illustratethat any one or all of the processor units can be placed in either aninput-output control mode or in a process mode according to therequirements of the application to which the array of FIG. 1B is put.

ARITHMETIC AND CONTROL REGISTERS

Referring now to FIG. 3, the principle registers and data paths of boththe control section and the arithmetic logic unit of the programmableunit of the present invention are illustrated. The ALU includes logicunit 31, A registers 32, B register 33 and true-false gates 34.

B register 33 is the primary interface between the programmable unit ofthe present invention and the main memory. This register also serves asthe secondary input to adder 30 and serves certain secondary functionsassociated with the arithmetic operations.

True-false gates 34 serve to provide the true contents of B registor 33or to provide the one's complement of the contents of the register 33.

A registers 32 are three functionally identical registers. Each of the Aregisters is used as a temporary data storage within a ALU and serves asa primary input to adder 30. Each of the A registers is loaded from theoutput of the barrel switches 31.

The control unit of the programmable unit of the present inventionincludes three basic sections: namely a section to provide an interfacebetween the ALU and the memory and peripheral devices, a section tohandle the decoding of M instructions and a section to receive and routethe N instruction control signals.

The output from the ALU is from barrel switches 31 and may be suppliedto interface register 48, register base register (RBR) 45 and memoryinformation register (MIR) 47 as well as to the alternate microprogramcount register (AMPCR) 41. The output of barrel switches 31 may also besupplied to shift amount register (SAR) 44.

Interface register 48 serves to receive addresses and other informationfor transfer either to memory address register (MAR) 49 or to counter30. Register base register (RBR) 43 contains the base address of a 256word block of main memory. The contents of this register areconcatenated with MAR 49 to form an absolute memory address. Associatedwith RER 43 is Base Register 2 (BR2) 46 which may contain the baseaddress of a 256 word block of main memory or the most significant partof a device address. As in the case of the contents of RBR 45 thecontents of BR2 46 are concatenated with the contents of MAR 49 to forman absolute memory address or a device address. Memory informationregister (MIR) 47 is used to buffer information being written to themain memory or to a device. This register is loaded from the output ofbarrel switches 31.

The contents of the microinstruction are received by microinstructiondecoder 40 to address the H memory and for transfer to literal register51, shift amount register (SAR) 44 and to alternate microprogram countregister (AMPCR) 41. Literal register 51 is used as a temporary storagefor literals in the M instructions which are to be used as inputs toadder 30, to counter register 30, or to memory address register 49. Theshift amount register 44 holds either the shift amount count or the wordlength complement thereof to be employed in controlling the number ofbits by which data is shifted in barrel switches 31. The alternatemicroprogram count register 41 contains the jump or return address forprogram jumps and subroutine returns within M programs. The address inthis register is usually one less than the position to be returned to.This register can be loaded from microprogram count register 42, fromthe barrel switch output or from M instruction decoder 40. Inassociation with this register is the microprogram count register (MPCR)42 which is the instruction address counter for the M memory. It usuallycontains the current M instruction address.

The N instruction decode is performed by test logic circuitry 53 and thecommand register 52. The functions of these latter circuits will be morethoroughly described below. One comment at this point, however, will bethat test logic circuit 53 receives information from condition register54, the contents of this latter register being a set of testable bitswhich act as error indicators, interrupts, local and global Booleanvariables and lockout indicators. These various condition register bitswill be thoroughly described below.

OPERATIONS UNDER CONTROL OF M INSTRUCTIONS

Before the formats of the M and N instructions are described, adescription of the principle operations to be carried out within theprogrammable unit will now be given. It will be understood that theoperations carried out within the programmable unit are initiated by theM instructions.

MEMORY AND DEVICE OPERATIONS

The memory and device operations are used to transfer data betweenprocessor unit and memory or some other device. The processor unit isconnected to the memory modules and devices through a switch interlockby bidirectional busses. Memory and device addresses are sent from theprocessor units memory address register (MAR) to the switch interlockand after connection onto the selected memory or device. Data receivedfrom a memory or the device is placed in the B register by designatingthe B register to the external data bus. Data sent to memory or thedevice is sent by way of the memory information register (MIR). Eachmemory or device operation is initiated in the first clock period of theM instruction and continued in parallel with subsequent M instructionexecutions. Thus, the memory and device operations may be totallyoverlapped by logic unit operations. The memory, device and setoperations, as a group, may be specified as either conditional orunconditional within each M instruction. The specific memory and deviceoperations will be more specifically described below.

LOGIC OPERATIONS

Each M instruction may contain exactly one logic operation. Theseoperations include binary Boolean operations between the A and B andbetween the B and Z inputs to the ALU, and most of the binary Booleanoperations between Z and A. There also are several ternary Booleanoperations among all three inputs and true add operations between anypair of inputs. The logical form of the various Boolean operations orBoolean connectives are illustrated in the table of FIG. 20.

The true add operations perform two's complement addition between the Aand B inputs to the ALU. The same operations can be made availablebetween B and Z inputs and between Z and A inputs if required. The finalcarry out of the most significant position of the ALU is available fortesting on the next M instruction and also is saved in the overflow bitof the condition register for later testing.

The ALU is formed of a plurality of basic logic units according to thedata path width chosen for a particular programmable unit. The number ofbits in a basic unit is chosen to be eight. Add operation variance arisefrom the choice of carrys to each eight bit group. For each eight bitgroup the logic unit can be wired so that the carry in is either thecarry out of the group immediately to the right or a constant. Thischoice cannot be changed by program. The carry in, however, can beeither enabled or inhibited by program. The usual configuration has allbut the rightmost eight bit group receiving its carry in from the groupto the right. The rightmost groups has a constant one carry in. Thecarry enables for all but the rightmost group are specified togetherwith the one carry in to the least significant position specifiedseparately.

BARREL SWITCH OPERATION

There are four barrel switch operations that can be specified and onemust be specified. These operations are: do not shift, shift rightcircular the amount in the SAR, shift right end off the amount in theSAR, and shift left end off the two's complement of the amount in theSAR.

Another type of operation which is performed under the control of Minstructions are the Set operations which are used to interrupt otherprogrammable units in an array of such units, to lock out and unlockcritical sections of such an array, and to set local condition bits. Inaddition, the M instructions contain various types of information whichwill be more thoroughly discussed below in relation to the format of theM instruction and other instructions.

INSTRUCTION FORMAT AND CONDITION REGISTER

There are four sources of control information embodied in theprogrammable unit of the present invention. These include the threelevels of instructions, namely, the S instruction, the M instruction andthe N instruction and also include a set of conditional bits placed inthe condition register 54 as illustrated in FIG. 3. These informationsources will now be described.

S INSTRUCTION FORMAT

Referring now to FIG. 13, a type of S instruction format will bedescribed. It is to be understood that no single S instruction format isto be preferred in the present invention. Thus, a variety of instructionformats may be employed, the only requirement being that particularstrings of M instructions are provided in the M memory to decode orinterpret each particular set of S instructions. It will be furtherunderstood that a plurality of such M instruction strings will reside inthe M memory.

The particular instruction formats illustrated in FIGS. 13A, 13B and 13Care adapted for the control of input-output data transfers; however, itwill be understood that these instruction formats also may be employedto specify routines to be carried out with the programmable unit of thepresent invention.

The input-output descriptor of FIG. 13 comprises 96 bits arranged inthree segments. The operation segment of FIG. 13A is divided into twofields. Field I specifies the operation to be performed while Field IImay be employed to specify the address of the peripheral device or theparticular memory module to or from which data is to be transferred.Field III of FIG. 13B is a character of 8 bits which may be used as acomparison character to terminate a data transfer. Field IV constitutesa counter which specifies the number of data segments to be transferredand which count is to be decremented by one and tested for zero uponeach data transfer. Field V is a set of control bits such as flags whichmay be used to modify the data transfer or specify various conditions.Field VI is an instruction counter which specifies the absolute addressfrom which the next descriptor operation is to be obtained. Field VII ofthe Control II segment of FIG. 13C is employed to specify the address inmemory to or from which the data is transferred. Field VII may bedivided into sub-fields to specify for example, a base address and arelative address position. In the Control II segment, bit 64 is employedto specify that the current channel whose operation is governed by thedescriptor is busy, bit 65 is employed to prohibit the currentdescriptor from initiating a new I-O sequence on another channel and bit95 is a parity bit.

The instruction formats of FIG. 13, as thus described can be employed tocontain information required for a particular channel operationincluding the provision for addressing a new set of descriptorinstructions for initiating a new operation on that channel when thecurrent operation has been completed. While the instruction format ofFIG. 13 has been described in relation to an I-O descriptor, this formatmay also be employed for other routines. In any case, this descriptorformat is implemented by the programmable unit of the present inventionby the receipt of Field I by the B Register 33 of the arithmetic logicunit of FIG. 3, from which this field is transferred, through adder 30and barrel switches 31 to the AMPCR 41 so as to serve to address the Mmemory. At that address, a new address is found and read out tomicroinstructions decoder 40 of FIG. 3, which address specifies thebeginning location of the sequence of M instructions required toimplement the S instruction thus decoded.

M INSTRUCTION FORMAT

Having described how an S instruction is decoded to obtain a sequence ofM instructions which implement the S instruction, the M instructionformats will now be described in reference to FIG. 14.

Each M instruction requires one sixteen bit word of storage in themicroprogram memory or M memory. There are two types of M instructionseach of which are differently decoded by the N instructions. The firsttype of M instructions specify at least one of six functions; acondition, a logic unit operation, a memory or device operation, a truesuccessor, a false successor and literals within the instruction. Thecondition and successors must be present in every M instruction;however, the other functions are optional, but all options can beincluded in the same instruction. A second type of M instructioncontains only instruction literals.

The first type of M instruction is represented by the format of FIG.14A. In this format, the zero bit is ONE and the remaining bits specifya N memory address at which may be found the appropriate N instructionwhich contains the operation and condition control bits specified bythis first type M instruction.

The second type of M instruction is represented by the formats of FIGS.14B and 14C. In FIG. 14C, the first three significant bits are all ZEROSindicating that the remaining bits 3 - 15 are a M memory address to betransferred to AMPCR 41 of FIG. 2. If either of bits 1 and 2 is a ONEand bit zero is a ZERO, then the format is as illustrated in 14B, wherebits 3 - 7 represent a SAR content field when bit 3 is a ONE and bits9 - 13 represent a literal field when bit 2 is a ONE. Bit 8 may be ineither the SAR content field or the literal field if both are notspecified; however, when bits 2 and 3 are both ONEs, then bit 8 isconsidered to be a part of the SAR content field.

There are sixteen testable conditions, exactly one of which must betested for each M instruction. If the test is successful, the entireinstruction will be executed and the true successor is taken as the nextinstruction address. If the test fails only the unconditional portionsof the instruction will be executed and the false successor will betaken as the next instruction address. The sixteen conditions which canbe tested include the twelve condition register bits and four otherconditions which are overflow, exclusive OR, least and most significantbit outputs from the adder on the previous M instruction.

The logic unit operations specified by the M instructions include theselection of the inputs to the adder, the adder operation, the barrelswitch operation, and the specification of the destination for theoutputs from the adder and barrel switches which destination either maybe in the ALU or in the control unit. The controls for the literal,counter, and shift amount register and controls to alter instructionsalready in progress also are included in this group.

The specific arithmetic and logic operations, as well as memory anddevice operations and set operations were discussed above in a sectionon Operations Under the Control of M Instructions. While these generaloperations will not be repeated here, there are certain specificfunctions which are under the control of the M instructions which shouldbe described. Among these are the routing of data segments not only tothe A and B registers of the ALU but also to such remote destinations asthe AMPCR 41, MIR 47, RBR 45, Counter 50 and MAR 49 as illustrated inFIG. 2. The M instructions also control the transfer of the contents ofliteral register 51 to Counter Register 50 and incrementation of CounterRegister 50. If the incrementation of Counter 50 causes the counter tooverflow and reset to all zeros, then the counter overflow bit ofcondition register 54 is set. These routing functions are performed byaddressing appropriate N instructions containing the required controlsignals.

Within each M instruction, the content of the SAR 44 must be specifiedas one of the following choices: the same as the content on the previousinstruction, the wordlength complement of the content of the previousinstruction, the value of the rightmost six bit output from barrelswitches 31 on the previous instruction, or a literal value from the Minstruction. This specification is acted upon before rather than afterthe shift takes place in barrel switches 31.

The M instruction also allows for two replace operations which permitpartially executed instructions to be modified. These operations dependupon the condition test and include the replacement of the destinationor a replacement of the instruction. In the case of a replaceddestination operation, a successful condition test allows the previousinstruction to be completed, however, if the condition test fails thenthe current instruction acts a null operation. In the case of a replaceinstruction operation, if the condition test is successful, then theprevious instruction is discontinued after one clock and the currentoperation is executed; however, if the condition test fails then thecurrent instruction acts as a null operation.

There are twelve memory and device operations any one of which may beinitiated by a given M instruction. These operation include: lock todevice for read, lock to device for write, unlock the memory or devicereserved for reading, unlock the memory or device reserved for writing,read (when a device has already been locked for reading), write (when adevice has already been locked for writing), register read, registerwrite, and stack AMPCR in M memory.

As has been indicated above, each M instruction must specify the next Minstruction address or successor in the M memory in one of two ways, onefor the condition test true and one for the condition test false. Ifboth specifications are the same, then the successor is unconditional.MPCR 42 of FIG. 3 usually contains the address of the currentinstruction. AMPCR 41 of FIG. 3 usually contains the address of thealternative instruction minus one. There are seven choices for eachsuccessor: step to the next instruction in sequence (the nextinstruction address is the content of MPCR plus one and the MPCR contentis replaced by the next instruction address), skip the next instruction(this operation permits one instruction conditional branch within anexplicity adder specification; the next instruction address is thecontent of the MPCR plus two and the MPCR content is replaced by thenext instruction address), repeat the instruction again (this operationpermits the repeated execution until the value of a condition changes;the next instruction address is the content of the MPCR which remainsunchanged), save loop address (this causes the address of the currentinstruction to be saved in the AMPCR so that jumps can later be made tothe current instruction address plus one), execute an instruction out ofsequence (this operation permits the instruction specified in AMPCR tobe executed with immediate return to the normal sequencing), call aprocedure (this operation causes a jump to a routine specified in AMPCRwith the current position saved for later return), and jump (thisoperation permits transfer of control to the instruction specified inAMPCR).

There are three literals which may occur in the M instructions: Minstruction addresses, data literals and shift amounts, For type oneinstructions, no additional time above the logic unit time is requiredto process the literals. For type two instructions comprised entirely ofliterals, no more than one clock is required. The M instruction addressliterals are those addresses requiring a full M instruction work whichtherefore, cannot be used with type one instructions or with otherliterals. Data literals may be used in type two instructions eitheralone or together with a shift amount. The data literal is loaded intothe literal register 51 of FIG. 3 before any logic unit operation in theinstruction is performed. The shift amount literals are loaded into SAR44 of FIG. 3 before any logic unit operation in the instruction isperformed.

CONDITION BITS

As indicated above, one of the four sources of information in theprogrammable unit of the present invention are those external conditionsignals supplied to condition register 54 of FIG. 3. Since thesecondition bits affect the implementation of M instructions by the Ninstructions, the respective conditions represented by these bits willbe described before a description is given of the format of the Ninstructions.

As has been indicated above, the condition register is the set of twelvetestable bits which act as error indicators, interrupts, local andglobal Boolean variables, and lockout indicators. The format of thecondition register is illustrated in FIG. 16.

Counter overflow bit (COV) is a bit which is used to remember overflowsfrom counter register 50 of FIG. 3. This bit is set whenever anincrement counter operation causes the counter to reset to all zeros.The bit is reset whenever it is tested. It is also reset whenever thecounter register is loaded from either the barrel switch output orliteral register 51 of FIG. 3. If it is set and reset in the same clockperiod, the reset will dominate. Any test on this bit actually tests the"logical OR" of this bit with the true overflow from the counter.

Read complete bit (RCC) is a bit which indicates that data is availableto the clocked into the B registor. This bit is set by the memory moduleor the device to which the programmable unit is read connected. Alldevices will set this bit. The read complete bit is reset by testing.

Memory address register ready bit (MAR) is a bit which is used toindicate that the MAR may be reloaded. It is set by the switch interlockor a device during a lock, read or write operation. The bit is reset bytesting. As long as the bit remains reset after the above operations areinitiated, it indicates that the device or memory module is busy.

Error in device or memory module for read (ERR) is a bit which indicatesthat an error has been detected in the memory module or device attachedto the programmable unit for a read operation. The bit is set by thedevice or switch interlock and reset by testing. The bit represents thelogical OR of all error signals from the device which require immediateattention. This includes memory parity errors, invalid addresses inperipheral memories, device or memory not connected (a signal from theswitch interlock), and power failure in the device. Conditions, such as"high speed printer out of paper" warning, are not included (some typesof device errors go only to the display).

Error in device or memory module for write (ERW) is a bit which actslike ERR except that it is associated with the memory module or deviceattached to this programmable unit for a write operation.

First external request bit (EX1) is a bit which indicates a new requestfrom an external device or another programmable unit. Such requestscould normally be serviced by any programmable unit. The bit issimultaneously set in all programmable units by the device. It is resetlocally within each programmable unit by testing.

Second external request bit (EX2) is a bit which indicates a requestfrom a device which is busy but not locked to any programmable unit.Indications would include such conditions as "tape-up-to-speed" from amagnetic tape unit. In this case only the programmable unit whichinitiated the tape operation would be expecting a return.

MIR ready bit (MIR) indicates data received by memory or a device aftera write operation. This bit is reset locally within each programmableunit by testing.

First global condition bit (GC1) is a bit which when set indicates asuccessfully perfomed lockout. The bit can be set in at most oneprogrammable unit at a time. It is set and reset locally within eachprogrammable unit. Testing this bit does not reset it.

Second global condition bit (GC2) provides a similar function as doesthe first global condition bit (GC1).

First local condition bit (LC1) is a bit which is used for temporarystorage of Boolean conditions within a programmable unit. It is setlocally by the programmable unit and reset locally by testing.

Second local condition bit (LC2) is similar to the first local conditionbit (LC1). The specific assignments for the condition bit can be changedfor special purpose systems. With the exception of the global conditionsbits, all bits are identical except for their external connections. Onlythree (MIR, LC1, LC2), however, can be set locally.

N INSTRUCTION FORMAT

Referring now to FIG. 15, the N instruction format will be described.This format is comprised of various control signals required toimplement the M instructions which have been described above. It will beunderstood that the N instruction format comprises control signals,which signals are now generated directly by circuitry but are stored inan instruction form in the N memory to be retrieved as required whichretrieval is in accordance with the N memory address contained in a typeone M instruction. While the preferred embodiment of the presentinvention utilizes the various bits of the N instruction directly ascontrol signals, it is within the scope of the present invention thatthe various bits of the N instruction can be in encoded forms thevarious combinations of which will designate the generation of theappropriately required control signals.

As indicated in FIG. 15, an implementation of an M instruction occursduring three time phases. Thus, the control signals designated by the Ninstruction are segregated into three groups: namely those required tobe employed during phase 1, those required to be employed during phases2 and 3, and those required to be employed during phase 3.

The timing relationship between the various phases will be morethoroughly described below in relation to certain timing waveforms;however, these phases will now be generally dscribed to the extent thatsuch description lends better understanding to the various controlsignals comprised in the N instruction format of FIG. 15.

As indicated above there are three timing phases and also there are twotypes of M instructions. Type one instructions will always have havephase 1 and phase 3 control signals, and in some cases may have phase 2control signals. Type two instructions have only phase 1 controlsignals. The phase 1 control signals of type two instructions areapplied to load the literals to AMPCR, LIT, or SAR as specified. Typetwo M instructions always require one clock time and always overlapphase 2 of the preceding type one instructions.

Phase 1 occurs in every type one instruction and requires one clocktime. It always overlaps phase 3 of the preceding type one instruction(there may be intervening type two instructions). Phase 1 is used forcondition testing, next instruction address computation, initiation ofmemory and device operations, loading instruction literals into the LITor SAR, and setting up for a logic unit operation.

Phase 2 occurs in some type one M instructions and requires a variablenumber of clock times. It is used to delay phase 3 for carrypropagation, instruction buffering, instruction modification, and typetwo M instruction execution. When the next M instruction is type two,the current type one M instruction is held in phase 2 for one clock timewhile the type two M instruction is performed. Phase 3 occurs with everytype one M instruction and requires one clock time. It is always phase 1of the next type one M instruction (there may be intervening type twoinstructions). Phase 3 is used to perform the logic unit operationsincluding destination selection.

The various control signals of the N instructions may be divided intofive groups depending on the phase in which they are executed.

CONTROLS USED ONLY IN PHASE 1

These controls are executed directly from the M instruction. Thecondition testing, conditional-unconditional specifications, replaceoperations, successor operations, initiation of memory or deviceoperations, condition bit setting SAR specifications comprise thisgroup.

CONTROLS USED IN PHASE 2

Only the logic unit operations (excluding destination selection) areperformed in phase 2. Depending on the width of a true add operation,the clock rate of the programmable unit and whether the barrel switchoutput is required, two rather than one clock times may be required tocomplete the logic unit operation. In such cases, a one-clock-time phase2 is included. The need for the addition of time is explicitly indicatedin the instruction during the duration control.

When the fetching of the next instruction from the M memory is delayed,the type one instruction currently being exectued (there always is one)remains in phase 2 until the fetch can be made. The need for theduration of this delay is not determinable by the programmer and isindicated dynamically by the microprogram buffer or the M memory.

When the next M instruction contains a replace operation the currenttype one instruction is held in phase 2 for one clock time to permitexecution of phase 1 of the replace operation. The need for this delayis determined by the replace controls in the next instruction.

CONTROLS USED IN BOTH PHASE 2 AND PHASE 3

These controls are executed from the command register. This group isconcerned with only the logic unit operation and consists of the Aregister selection, the B register selection, the C input selection, theadder operation and barrel switch operation.

CONTROLS USED ONLY IN PHASE 3

These controls are executed from the command register. This group iscomprised of the A register destination, the B register destination, theremote destination, and the literal transfer and counter operations.

The literals in the M instructions are loaded into the specifiedregister (AMPCR, SAR, or LIT) during the first clock of the instruction.For type one instructions, this is phase 1; for type two instructionsthis is phase 2 of the type one instruction then being executed.

A table of the more important control bits (or signals) which areincluded in the N instruction format are presented in FIG. 20 along witha list of their functions.

External Controls set the condition register bits and are initiated byexternal devices, memories and other programmable units.

The specific individual control signals will be more thoroughlydescribed below in relation to the various circuits to which thosecontrol signals are supplied.

DETAILED DESCRIPTION OF SPECIFIC CIRCUITS

In FIG. 3, there is presented a diagrammatic representation of the ALUof the present invention which is a more detailed representation thenwas generally provided in FIG. 2. It will be remembered that a featureof the present invention is the provision of arithmetic and logiccircuitry formed of a plurality of modular logic units. The circuitry ofFIG. 3 includes a logic system arranged in what will be called a sectioncomprised of two half sections 60 and 61. Each half section is adaptedto receive, in parallel, data segments of eight bits. Thus, the logicsection illustrated in FIG. 3 is adapted to receive data segments ofsixteen bits. As further illustrated in FIG. 3, each logic half section60 and 61 is respectively under the control of logic controls 68 and 69which in turn are activated by control signals received from N decoder55 of the control portion of the programmable unit as illustrated inFIG. 2.

Logic half section 60 includes logic groups 64 and 65 as well as carryunits 74 and 75. Similarly, logic half section 61 includes logic groups66 and 67 as well as carry units 76 and 77. Each logic group is adaptedto receive input data segments of four bits. As illustrated in FIG. 3,each carry unit performs a carry look-ahead function for itscorresponding logic group. In addition, the carry-look-ahead functionfor each half section 60 and 61 is provided by carry look-ahead halfsections 80 and 81, respectively.

The remaining portion of the ALU illustrated in FIG. 3 includes Aregisters 32 and the B register (and true-false gates) 33. The Aregisters 32 can be set under the control of A register controls 70 and71 and the B register is under the control of B register control 72. Thetrue-false gates which will be discussed below are under the control ofsignals received from the control portion of the system by way ofcontrol bus 73 as illustrated in FIG. 3.

Where appropriate, the same numerals have been employed in both FIGS. 2and 3 to identify those registers appearing in both figures.

Referring now to FIG. 4, an alternative ALU will be described which isformed of two logic sections or four half logic sections. With thisformat, the ALU can receive data segments of thirty-two bits. As withthe embodiment illustrated with FIG. 3, each of the logic half sections60 . . . , 63 has associated with it the respective half section carrylook-ahead 90 . . . , 93. The interconnection between the variouslook-ahead half sections differ from that of the embodiment of FIG. 3 ina manner which will now be briefly described. Each half sectionlook-ahead receives group signals from the two carry units in thecorresponding logic half section as illustrated in FIG. 3, and returnsgroup carry signals to those carry units. In addition, each half sectioncarry look-ahead generates section transmit and section generate signalswhich are sent to each half section carry look-ahead in the system whichis the most significant one of each pair of half section carrylook-aheads. Thus, in FIG. 4, the most significant of each pair of carrylook-ahead half sections are carry look-ahead 90 and 92, while therespective carry look-aheads 91 and 93 are the least significant of thepair in which they reside. Conversely, the least significant of eachpair will generate groups signals which are transmitted to the mostsignificant of that pair. As indicated in FIG. 4, the section signalsgenerated by the most significant one of the pair are transmitted to theother most significant ones of the pairs by connection 94 and 95 whilethe group carries between half sections are transmitted from the leastsignificant ones of the pair to the most significant ones of that pairby connections 96. In FIG. 3, where only one pair of half sections hasbeen employed, the group signals transmitted between half sections areagain transmitted by way of connection 82 from the least significant oneof the pair to the most significant one. As further illustrated in FIG.3, the section carry signals are really employed by the half sectioncarry look-ahead which generates those signals.

Other distinctions exist between the different embodiments respectivelyshown in FIGS. 3 and 4. One is the manner in which the different controlsignals are employed to activate different logic half sections. In theembodiment of FIG. 3 each logic half section is provided with its ownlogic control unit and thus each logic half section can be separatelyemployed. In the embodiment of FIG. 4, the most significant half section60 and the least significant logic half section 63 are each providedwith separate controls 98 and 99, respectively. The intermediate halflogic sections 61 and 62 are provided with the same sets of controlsignals from the intermediate control 97. Each of the respective logiccontrols are activated in response to control signals received from thecontrol portion of the system in accordance with the format of therespective N instructions, as will be more thoroughly discussed below.

As indicated in FIG. 2, the adder or logic is also provided with a thirdinput namely a Z input. As indicated in both FIGS. 3 and 4, the X inputsare the contents received from counter register 50 of FIG. 2 whichcontents are supplied to the most significant logic half section and thecontents received from literal register 51 of FIG. 2 which contents aresupplied to the least significant logic half section.

The logic groups are represented in FIG. 3 and implied in FIG. 4 areidentical. The circuitry of an individual logic group is illustrated inFIG. 5 and will now be described. In essence, the circuit of FIG. 5comprises a plurality of AND gates and NOR gates. It will be noted thatcircuitry of FIG. 5 can be divided into four sets of circuits each ofwhich is adapted to receive inputs of data bits of different significantlevels and also to receive the respective control signals C₁ . . . . C₇.The intermediate outputs X, Y, K' and their complements are receivedfrom the first level of gates and are supplied to the second level ofsuch gates to provide a generate signal, transmit signal and sum signalfor each of the four significant bit sections. The respective Booleanequations implemented by the circuitry of FIG. 5 are listed in FIG. 5.

The A input signals are those signals which are received from the Aregisters as will be more thoroughly described below. The B signals arethose signals received from the B register or their complements. The Zinputs are those inputs received either from counter 50 or literalregister 51 of the control portion of programmable unit as illustratedin FIG. 2. The inverse carry signals K received from the respectivecarry look-ahead circuits which will be more thoroughly described below.The respective S signals are the logic output signals which are suppliedeither to barrel switches 31 or to B register 33 as indicated in FIG. 2.The G signals and T signals are signals which are supplied to therespective carry look-ahead circuits that, in turn, generate the K carrysignals described above.

It will be understood that the S output signals will represent differentBoolean expressions in accordance to the particular selected controlsignals C₁ . . . . C₇ presented to the logic group of FIG. 5 in responseto presentation of N signals to logic controls 68 and 69 of FIG. 3. TheN signals are received from N Decoder 55 of FIG. 2 and implement apre-given N instruction.

It will be appreciated from a review of FIG. 5 that each significant bitsection of the logic group illustrated in that FIGURE must receive acarry signal from the previous section and apply the carry signal to thenext section in order. The group carry look-ahead circuitry whichprovides these signals is illustrated in FIG. 6, which will now bedescribed. The circuitry is adapted to receive a carry signal GC in fromthe next least significant logic group by way of the half section carrylook-ahead circuitry that will be described below. This circuitry alsoreceives the various bit transmit signals BT and bit generate signals BGfrom the respective sections of its associated logic group. Thegeneration of these signals was described in relation to FIG. 5. Uponreceipt of these signals the circuitry of FIG. 6 in turn, generates theappropriate inverse carry signals BC which are supplied to the varioussections of the associated logic group as the carry signals K asindicated in FIG. 5. As further illustrated in FIG. 6, this circuitryalso generates the inverse group transverse signal GT and the inversegroup generate signal GG which signals are supplied to the carrylook-ahead half section as has been indicated in FIG. 3 and which willbe more thoroughly described below. The respective Boolean equationsrepresenting the functions implemented by the circuitry of FIG. 6 areillustrated in FIG. 6. The circuitry of FIG. 6 is just that circuitry ofthe respective carry units 74 . . . , 77 which are illustrated in FIG.3.

The carry look-ahead half sections 80 and 81 as illustrated in FIG. 3and 90 . . . , 93 as illustrated in FIG. 4 are shown in detail in FIG. 7which will now be described. As indicated in FIGS. 3 and 4, each halfsection carry look-ahead will receive or not receive signals from thenext least significant half section carry look-ahead, depending uponwhether it is the most significant or least significant half sectioncarry look-ahead of the logic section of which it is a part. Conversely,each half section carry look-ahead will transmit different types ofsignals to the other carry look-ahead half sections depending upon itsplace in the hierarchial order. The circuit of FIG. 7 is adapted toreceive and supply the various required signals regardless of its orderin the hierarchy. Therefore, certain connective leads as illustrated inFIG. 7, will or will not be required. Thus, the circuit of FIG. 7 isadapted to receive inverse group generate signals GG which arerepresented as having odd numbered subscripts when they come from a lesssignificant group of carry units and are presented to have evensubscripts when they come from a more significant group carry unit. Thecircuit is also adapted to receive inverse group transmit signals GTwhich are also provided with odd and even numbered subscripts inaccordance with the convention just described. In return, the circuit ofFIG. 7 generates group carry signals GC which are also provided with oddor even numbered subscripts depending on their significance, thesesignals being supplied to the respective group carry units asillustrated in FIG. 3. When the half section carry look-ahead is a lesssignificant one, it is adapted to supply the next most significant onewith the group transmit signals GT and group generate signals GG. Whenthe circuit is a most significant half section look-ahead it suppliesthe respective section transmit signals ST and section generate signalsSG to all the more significant carry look-ahead half sections of the ALUas indicated in FIG. 4. Accordingly, the circuit of FIG. 7 is alsoadapted to receive such section generate and section transmit signalsfrom the other most significant carry look-ahead half sections to forman inverse section carry in signal SC_(in). It will be understood thatthis latter function will not be provided when the circuit is a lesssignificant half section carry look-ahead. Similarly, the circuit willnot be sensitive to group transmit and group generate signals from thenext less significant half section carry look-ahead and, in thissituation, the respective input leads provided for this function willhave ZERO or ONE binary signals permanently forced upon them asindicated in FIG. 7.

It will be noted that the generation of group carry signals to the leastsignificant bit positions of each logic half section can be inhibited bya control signals N₁₅ received from respective logic control 68 or 69 ofFIG. 3.

The respective Boolean equations representing the functions implementedby the circuit of FIG. 7 are listed in FIG. 7.

The various logic control units 68 and 69 of FIG. 3 and 97, 98 and 99 ofFIG. 4 will now be described in reference to FIG. 8. Such controls arebasically just standard decoders formed of a plurality of AND and NORgates. However, the circuitry of FIG. 8 is presented to provide a betterunderstanding of the various N control signals which are obtained fromrespective N instructions. The particular signals employed to controlthe respective logic groups of FIG. 3 comprise five N signals one ofwhich is an inhibit signal. Upon the decoding of the signals N₉, N₁₀,N₁₁ and N₁₂, seven subcontrol signals C₁ . . . , C₇ are generated andsupplied to the respective logic groups as indicated in FIG. 5 anddescribed in relation to that figure. An eighth signal N 15 is alsogenerated by the logic control of FIG. 2 and is supplied to the carrylook-ahead half section corresponding to the logic half section in orderto inhibit the generation of the least significant group carry signalfor that logic half section as described above in relation to FIG. 7.Another inhibit signal is employed to inhibit the generation of the C₅and C₆ signals. Referring briefly to FIG. 5, it will be noted that theC₅ and C₆ signals serve to implement the Z input to the logic group.Thus, the inhibit signal to the control circuitry of FIG. 8 serves toinhibit the Z input to the corresponding logic groups. The variousfunctions provided by the respective logic groups under control of Ncontrol signals is listed in FIG. 20 under the heading of AdderOperation.

Other examples of the manner in which the N control signals of the Ninstruction format are employed to control ALU operations areillustrated in FIGS. 9, 10 and 11 which respectively illustrate thecircuitry of the A registers, the B register and barrel switchoperations.

As illustrated in FIG. 9, the three A registers A1, A2 and A3 arecomprised respectively of three sets of flip-flops A₁₁ . . . A₁₈ ; A₂₁ .. . , A₂₈ ; A₃₁ . . . , A₃₈. As indicated in the table of FIG. 20, the Aregister inputs are under the control of two N signals N₂₁ and N₂₂ whichrespectively provide the function of keeping the A registers unchanged,providing an input to the A1 register, providing an input to the A2register and providing an input to the A3 register. As indicated in FIG.9, the respective control signals N₂₁ and N₂₂ are supplied to N decoder110 which in turn provides three output signals C₁₃, C₁₄, and C₁₅ whichare respectively supplied to the flip-flops of A1 register, A2 registerand the A3 register. These signals may be of the type which normallyurge the respective flip-flops to be reset at clock time thus preventingthe setting of the flip-flops and, thus, the function of the controlsignals N₂₁ and N₂₂ is to inhibit any one of the C signals thus allowingdata segments coming in over data bus 88 to be stored in any one of theregister set of flip-flops.

As indicated in the table of FIG. 19, the A register outputs are underthe control of the control signals N₁ and N₂ and serve to implement theread out of the A1 register, the A2 register and the A3 register or toprovide out all zeros. The manner in which these operations areimplemented is also illustrated in FIG. 9 where the control signals N₁and N₂ are supplied to N decoder 111 which in turn provides four outputsignals C₉ . . . , C₁₂. The signals C₉, C₁₀, C₁₁ are respectivelysupplied to AND gates to control the readout of the respectiveflip-flops of registers A1, A2, A3. However, the signal C₁₂ is suppliedto the plurality of one input AND gates which by their respective selveswill generate output signals that are inverted by the NOR gates asillustrated in FIG. 9 to provide ZERO outputs. The outputs of the NORgates are supplied by way of bus 84 to the respective logic groups ashas been illustrated in FIGS. 3 and 4 above.

Referring now to FIG. 10, the manner in which the control signalsgoverning the B register operations will be described. As indicated inthe table of FIG. 20, the B register inputs are controlled by three Nsignals, N₁₈, N₁₉ and N₂₀. In FIG. 10, these signals are supplied to Ndecoder 112 which in turn, generates the respective signals C₁₆ . . . ,C₂₁. It will be remembered from the earlier discussion of the B registerthat the B register can receive data from the main memory, from theadder, from the barrel switches and also receive four bit and eight bitcarries. Thus, signal C₁₆ serves to condition the appropriate AND gateto receive a signal over input lead 107 representing an eight bit carry,control signal C₁₇ serves to condition appropriate AND gate to receivethe signal over input lead 108 representing a four bit carry, signal C₁₈serves to condition the respective AND gate to receive data bits overthe respective input leads 106, signal C₁₉ serves to condition therespective AND gates to allow for the receipt of the eight bit datasegments for the respective leads 105 and signal C₂₀ serves to conditionthe respective AND gates to allow for the receipt of data bits over therespective leads 104. While the leads 104 are merely the connectors,they make up data bus 88 from the barrel switches which data bus alsoincludes the respective leads 106 from the adder output.. Thus, thedifferent C signals serve to gate the various incoming data bits to therespective flip-flops B₁ . . . , B₈ which form the B register. Asindicated in FIG. 10, the C₂₁ control signal serves to set therespective flip-flops at clock time.

As indicated in the table of FIG. 19 under the heading of B RegisterOutputs, these operations are controlled by control signals N₃ . . . ,N₈. These respective control signals are transmitted from the controlportion, of the programmable unit of the present invention, to thecorresponding gates in FIG. 10, the outputs of which form data bus 85which connects the B register to the respective logic units.

It should be noted in relation to both FIGS. 9 and 10 that the registersillustrated therein are only eight bits wide. However, it will beappreciated that the registers can be expanded to handle any particulardata width and that the only alteration that might be required would bethe provision of extra drivers to supply sufficient current signalswhich drivers would nevertheless be under the control of the respectiveN signals as has been described above.

FIG. 11 is a schematic diagram of the barrel switches, two of which areemployed in the present invention. These switches are of the typedisclosed in the Stokes et al application, Ser. No. 789,886, filed Jan.8, 1969, and assigned to the assignee of the present application. Thus,the barrel switches will not be discussed in detail except to indicatetheir control. The circuit of FIG. 11 is adapted to receive eight bitdata segments from data bus 83 and to shift such bits right or left byan amount specified by the contents of SAR 44 of FIG. 2. The signalsfrom SAR 44 are supplied to a decoder (not shown) which, under controlof signals N₁₆ and N₁₇ from the instruction, selects the appropriate oneof control lines C₂₂ . . . , C₂₉ as required to accomplish the desiredshift. Thus, if the SAR contents specify a shift of three bits and the Ninstruction specifies a right shift, the decoder will supply anappropriate signal to lead C₂₅ as indicated in FIG. 11. If the Ninstruction specified a shift left (of three bits), then the decoderwould supply a signal to lead C₂₇. The resulting shifted data segment isthen routed back to data bus 88. The operations specified by the N₁₆ andN₁₇ signals are listed in the table of FIG. 19 under the heading ofshift operations. It will be appreciated that the switch of FIG. 11 canbe expanded to receive data segments of larger number of bits when thedata path width of the programmable unit of the present invention is soexpanded.

Brief mention will now be made on FIGS. 19 and 20. As was described inrelation to the format of the N instruction of FIG. 15, this instructionis made up primarily of control signals which are required to beemployed during different phases of the operation of the programmableunit of the present invention which will be more thoroughly describedbelow. The three sets of section control or N signals are those employedin Phases 2 and 3, those employed in Phase 3 and those employed inPhase 1. FIG. 19 is a list of the N control signals which are employedduring Phase 2 and 3. FIG. 20 is a list of the principle N controlsignals employed during Phase 3.

As has been indicated in the earlier portion of this specification, theN instructions are retrieved from the N memory and are, in essence,decoded or implemented by the N decoder 55 as illustrated in FIG. 2.This circuitry is shown in more detailed form in FIG. 17 and will now bedescribed.

The N instruction of the format illustrated in FIG. 15 is received fromthe N memory output register 115 and transmitted to the variousregisters which serve to form test logic 53 as illustrated in FIG. 2. Asindicated by the instruction format of FIG. 15, the N instructionincludes Phase 1 control. Phase 2 and 3 controls and two other bitswhich specify a logic unit operation condition and a two clock timecondition. The specific Phase 3 controls and Phase 2 and 3 controls havebeen described above in some detail. However, the Phase 1 controls havenot been so described. Suffice it to say that Phase I controls are thosesignals which are required during the first phase of an instructionexecution and will now be described to the extent that such signals arerequired to implement the various condition registers of FIG. 17. Thus,one bit of the Phase 1 control field will specify whether or not thetrue or false states of the various condition bits of condition register54 are to be tested. This signal will be transmitted to conditionselector 118 by way of connector 142. Four other bits of Phase 1 fieldare employed to specify a particular condition to be tesetd from amongthe various condition bits of condition register 54 and these foursignals will be transmitted to condition selector decoder by way of busconnection 141.

Still another set of control bits in Phase 1 field are employed tospecify a new M instruction address and these bits are transmitted byway of connections 139 and 140 to the memory register control select 128which when conditioned by condition selector 118 will cause M programaddress register (MPAD) 129 to initiate a new address to be sent to theM memory by either MPCR 42 or AMPCR 41 of FIG. 2.

Phase 1 control field further includes bits specifying a memory or adevice operation or a set operation as was described in the aboveGeneral Description and these bits are transmitted by connectors 136 and137 to conditioning register 127 such that when an appropriate conditionis tested by condition selector 118, conditioning register 127 willtransmit this information to the switch interlock and also set conditiondecoder 120 to set the appropriate condition bit in condition register54. Another bit in the Phase 1 control field is one required to indicatea word complement of the contents of SAR register 44 of FIG. 2. This bitis transmitted to conditioning register 126 by connector 135 to activatethe complement in the SAR 44. When a logic unit operation is to beperformed, the appropriate bit in the N instruction format istransmitted by connector 132 to set condition registers 123 and 124 forthe transfer of the Phase 2 and 3 controls and the transfer of Phase 3controls to command register 52. When a two clock time instruction is tobe executed, this is indicated by the first bit of the N instructionformat and is transferred to AND gate 125 to be clocked to commandregister 52. The command register will now contain the appropriate Phase2 and 3 controls and Phase 3 controls that have been described above andare required to control the respective logic and destination operations.The other signals required to set the respective condition bits ofcondition register 34 include a signal from the switch interlock toglobal condition bit 121 to set the appropriate global condition bits incondition register 54. The other condition bits to be set are set bysignals received from the ALU or from the switch interlock as wasdescribed in the General Description above.

M instruction decoder 40 will now be described with reference to FIG.18. It will be remembered from the discussion of the M instructionformats of FIG. 14 that a ONE in the zero significant bit indicates atype one instruction which contains an N address and that a ZERO in thezero significance bit indicates a literal instruction or type twoinstruction in which bit positions 1 and 2 specify various literaloperations. In FIG. 18, these first three bits are tested by decoder151. If the zero significant bit contains a ONE, then the contents ofthe MPM register 150 are transferred to address the N memory. If thezero bit is a ZERO and the first bit is a ONE, then the literal field ofthe M instruction is transferred to literal register 51 of FIG. 2. Ifthe second significant bit position is a ONE then the contents of theSAR field as illustrated in FIG. 14 are transferred to SAR inputselector 153. If the first three bit positions are zero then theremaining portion of the M instruction is a new M address and istransferred to AMPCR 41 of FIG. 2. If the first and second significantbit positions are both ones, decoder 151 activates control gate 152 toset literal register 51 to receive a data segment of different numbersof data bits as was described in regard to the M instruction format inthe General Description above.

As was indicated above in the description of the N instruction decoder,the N instruction format contains certain bits in the Phase 1 fieldwhich are employed to specify data transfers to or from the programmableunit of the present invention. In order to better describe the manner inwhich such data transfers take place and also to illustrate the mannerin which data and the various instructions are placed in theirrespective memories, reference will now be made to FIG. 12 thatillustrates the switch interlock (SWI) which is indicated only generallyin FIG. 1A. As indicated in FIG. 12, data and/or instructions may besupplied or written into any one of the three memories 20a, 20b and 20cby way of memory instruction register 47 or AMPCR 41, which areregisters of the programmable unit as illustrated, from a peripheraldevice by way of switching unit 8 as indicated in FIG. 12 and also inFIGS. 1A and 1B. It will be noted that which register is connected towhich memory will be determined by the Phase 1 field of the Ninstruction controlling the data transfer. As further indicated in FIG.12, and has been described above, the N memory 20C is addressed from Mdecoder 40, the M memory 20b is addressed by the MPCR or the AMPCR byway of incrementer 43 and main memory or the S memory is addressed byway of MAR 49 when concatenated with register base register 45 or baseregister 46. The output of main memory 20a is to B register 33. Theoutput of M memory 20b is M decoder 40 by way of MP buffer 25.

Although MP buffer 25 has not been described above, it serves animportant function in allowing an entire string of M instructions to beretrieved upon the decoding of an S instruction thereby eliminating thetime delay that would occur if the respective M instructions were to beseparately addressed.

Although not explicitly shown in FIG. 12, it is understood that analternative data path can be provided from MIR 47, AMPCR 41 and SU 8directly to B register 33.

PHASE RELATIONS FOR M INSTRUCTION EXECUTION

As was indicated in the discussion of the M instruction format, thereare two types of M instructions: type one instructions which implementlogic and data transfer operations and type two instructions whichcontain litorals including a new M instruction address and shiftamounts. The type one instruction is executed in three phases, the firstand third of which each require one clock time with the second phaserequiring a variable number of clock times. The type two instruction hasonly phase 1 which requires one clock time.

Successive M instructions are executed in an overlapped manner and thisoverlap and other characteristics thereof will now be described withreference to FIGS. 21, 22 and 23.

FIG. 21 illustrates the overlap in execution of two successive Minstructions which shall be called Instruction A and Instruction B. Itwill be remembered that when the M instruction is of type one, thenthere is a corresponding N instruction to implement the various requiredoperations. As indicated in waveform b of FIG. 21, the address for thecorresponding N instruction A is transmitted to the N memory at thebeginning of clock period T₁. The N instruction A is received from the Nmemory towards the end of this clock period as indicated in waveform c.The selected conditions are tested (waveform d) and the inputs aresupplied to the MPAD register (waveform e). The output signals from MPADregister (waveform e) and the output of command register (waveform h)are generated at the beginning of clock period T₂. The command registeris now free to receive a new instruction and thus, during this sameclock period, a new address for the next Instruction B is generated asillustrated in waveform h. Instruction B is received out of the N memoryshortly before the end of clock period T₂ as indicated in waveform j.The other waveforms in FIG. 21 which indicate the setting of two clockflip-flops and various inhibit signals are not employed in thisoperation. It will be noted from FIG. 21 that the execution of the Phase1 controls of Instruction B occurred at the end of clock period T₂ andthus the Phase 1 controls of Instruction B are implemented during Phase3 of Instruction A.

Referring now to FIG. 22, the execution of a type one instruction inwhich Phase 2 requires two clock periods will now be described. Asindicated in FIG. 22, the respective waveforms b . . . , e are the sameas in FIG. 21 since they represent the retrieval of the firstInstruction A. In this case however, the retrieved N instruction formatwill contain a bit indicating a two clock time operation as has beendescribed above in relation to FIG. 17. This causes a two clock timeflip-flop to be set as indicated in waveform g of FIG. 22 and, as aresult, the output signals of MPAD register and the command register asrepresented in waveforms f and h are delayed for one clock period asrequired for the two clock time operation. Similarly, the addressing andreceipt of Instruction B from the M memory is also delayed for a clockperiod until the two clock time operation of Instruction A has beencarried out during clock periods T₂ and T₃, as indicated by waveform j.Phase one of Instruction B is therefore executed at the end of clockperiod T₃, the various clocks having been inhibited at the end of clocktime T₂. Phase two and/or three will be executed during T₄.

Referring now to FIG. 23, the timing relation between two successiveinstructions will now be described where the second M instruction Bcontains a literal and thus requires no N instruction. As indicated inFIG. 23, the first five waveforms (waveforms b . . . , f) are the samein FIG. 23 as in FIG. 21 and represent the retrieval and execution ofthe first phase of Instruction A. Furthermore, the output from thecommand register (waveform h in FIG. 21 and waveform g in FIG. 23) isinitiated at the beginning of clock period T₂. Furthermore, theaddressing of the M memory for Instruction B also occurs at the sametime in both figures. However, the receipt of M instruction (waveform iin FIG. 23) occurs earlier than does the receipt of the N instruction ofFIG. 21 (waveform j) and, since Instruction B is a literal in FIG. 23,no N instruction is required. This causes M decoder 40 of FIG. 2 togenerate a hold signal as indicated in waveform m of FIG. 23. As aresult, the output of command register (waveform g of FIG. 23) ismaintained while the literals of the M instruction B are transferred toa respective register as indicated by waveform i of FIG. 23. In virtualconcurrence with the hold signal of waveform m, the various phase clocksare inhibited as shown in waveform n to allow for the literal transfersat the end of clock period T₂. The literal transfers having occurred,the output of the command register then remains valid until the end ofclock period T₃ as indicated in waveform g. In this manner, theexecution of a type 1 M instruction has been delayed to allow forliteral transfers by the next succeeding type two instructions. Assumethe literal of the B Instruction specifies a new M address. Then theMPAD is forced as indicated in waveform j to again address M memory(waveform k) to retrieve a new instruction from M memory and then it's Ncounterpart from N memory as indicated in waveform e. The instructionfrom N memory is received at the end of clock period T₃ when the holdand inhibit signals are no longer up.

While the timing diagrams thus described represent only a few of thedifferent situations that arise during the execution of successiveinstructions in an overlapped manner, it is believed that the abovedescription will be sufficient to indicate how this overlappedinstruction execution takes place and also how, for example, differentliteral information may be replaced in the respective registers whenrequired for the execution of a conditional M instruction.

M INSTRUCTION SEQUENCES

While the significance of S instructions and N instructions have beenfairly well described above, the significance of the M instruction mayrequire more description. To this end strings or sequences of Minstructions are illustrated in FIGS. 24 and 25 and will now be brieflydescribed.

FIG. 24 illustrates a sequence of M instructions that would be employedin a particular input-output operation specified by an I-O descriptor ofthe type illustrated in FIG. 13. Each step of the sequence requires an Minstruction execution. These steps are: transfer contents of MAR to A2register; transmit "device write" signal and transfer the contents of A1register and least significant character of B register plus ONE to A1register; transmit "unlock device read" signal; read from device andshift contents of B register left 4 bits and place in A3 register; whenMAR is ready, transfer contents of A1 register plus ONE to A1 registerand MAR; when B register is ready transfer contents of B register to A2register and read from device; when MAR is ready, transfer contents ofA2 register to MAR; when B register is ready, transfer its contents toMIR; send MIR contents to memory and shift contents of A3 register right8 bits.

Another M string is illustrated in FIG. 25 which is adapted to implementa "string scan" routine specified by an S instruction. This routine isto find all starting positions of all matches of a pattern string in asource string. The legend in FIG. 25 lists which registers will containthe respective data segments that make up the source location S, patternlocation P, source contents SC, pattern content PC, match indication M,pointers SP, PP and MP and the register base registers.

While particular embodiments of the present invention have beendescribed and illustrated, it will be apparent to those skilled in theart that changes and modifications may be made therein without departingfrom the spirit and scope of the invention as claimed.

What is claimed is:
 1. A programmable unit including a logic unitcoupled to a plurality of registers for data transfer, said programmableunit comprising:circuit means coupled to said logic unit and registersto transmit thereto different specific sets of control signals; acontrol memory to store a plurality of different sets of controlsignals, said control memory being coupled to said circuit means; acommand memory to store a plurality of retrievable encoded operationalcommands some of which specify given ones of said sets of controlsignals; a command decoder coupled to said control memory and to saidcommand memory to retrieve given ones of said specific sets of controlsignals to condition either said logic unit or said registers; clockmeans coupled to said command decoder to generate timing pulsesrepresenting phases during which said sets of control signals areimplemented; and addressing means coupled between said command decoderand said control memory and adapted to retrieve a set of control signalsduring the implementation of a previous set of control signals.
 2. Aprogrammable unit according to claim 1 including:delay means coupled tosaid clock means to inhibit certain timing pulses to inhibitimplementation of said previous set of control signals to allow forretrieval of a new command instruction.
 3. A programmable unit includinga first memory to store instructions specifying routines and a secondmemory to store sets of operational command instructions, saidprogrammable unit comprising:first means coupled to said first memoryand adapted to receive one of said routine instructions; second meanscoupled to said first means and to said second memory and responsive tothe receipt of said routine instruction to address said second memoryand receive a command instruction, said second means includingaddressing means adapted to retrieve a command instruction during theimplementation of a previous command instruction; clock means coupled tosaid second means to generate timing pulses representing phases duringwhich said command instructions are implemented; and delay means coupledto said clock means to inhibit certain timing pulses to inhibitimplementation of said previous command instruction to allow forretrieval of a new command instruction.
 4. A programmable unit accordingto claim 3 including:a plurality of registers for data transfer; acommand decoder coupled to said second memory and to said plurality ofregisters to receive said command instructions from said second memoryto activate data transfer between selected ones of said registers.
 5. Aprogrammable unit according to claim 4 including:a literal registercoupled to said second memory and adapted to receive data literals fromsaid second memory.
 6. A programmable unit according to claim 4including:an external peripheral device; and a peripheral communicationbus coupled to said external peripheral device; at least one of saidregisters being coupled to said peripheral communication bus toimplement data transfers to or from said peripheral device; said commanddecoder being adapted to receive from said second memory certainsequences of command instructions to specify logic operations and othersequences of command instructions to specify data transfers to or fromsaid peripheral device.
 7. A programmable unit according to claim 3wherein:said first means includes a register to receive routineinstructions in response to the receipt of a command instruction by saidsecond means.
 8. A programmable unit including a plurality of registersfor data transfer, said programmable unit comprising:circuit meanscoupled to said registers to transmit thereto different specific sets ofcontrol signals; a control memory portion to store a plurality ofdifferent sets of control signals, said control memory portion beingcoupled to said circuit means; a control memory addressing means coupledto said control memory portion to retrieve given ones of said specificsets of control signals; and clock means coupled to said circuit meansto generate timing pulses representing different phases during whichsaid sets of control signals are implemented.
 9. In a programmable unitincluding a first memory portion, a second memory portion, and aplurality of registers for data transfer, a method comprising:storing aplurality of retrievable encoded operational commands in said firstmemory portion, some of which commands specify given sets of controlsignals; storing said given sets of control signals in said secondmemory portion; retrieving given ones of said commands from said firstmemory portion to specify retrieval of said given sets of controlsignals from said second memory; transmitting one of said given sets ofcontrol signals to said registers to condition them for operation; andgenerating a plurality of distinct timing phases for each of said one ofsaid given sets of control signals, said registers being conditioncorresponding to each individual set of said one of said given sets oftransmitted signals during distinct ones of said generated plurality ofdistinct timing phases.
 10. The method of claim 9 further including thestep of:overlapping the implementation of an individual set of said oneof said given sets of transmitted control signals with an individual setof another of said given sets of transmitted control signals.
 11. In aclock controlled programmable unit including a first memory to storesets of instructions specifying routines, a second memory to storeoperation command instructions to implement said routine instructions,an address register coupled between said first and second memories, athird memory to store control instructions to implement said commandinstructions, a decoder coupled to said second and third memories toreceive command instructions and to access said third memory, and aclock inhibit means coupled to said decoder, said respectiveinstructions being formed of sets of signals; the method comprising thefollowing steps:storing, in said second memory, a first set of signalsrepresenting a first command instruction which when fetched from saidsecond memory to said decoder will effect an operation to be executed bysaid programmable unit; and storing, in said second memory, a second setof signals representing a second command instruction which when fetchedfrom second memory to said decoder will effect a delay of said operationexecution by at least one clock time.
 12. A method according to claim 11wherein said programmable unit further includes a condition registercoupled to said decoder, which condition register may reside in aplurality of condition states, and wherein:the second storing stepincludes the storing of a second set of signals which, when fetched fromsaid second memory, effects a testing of said condition register todetermine its state.
 13. A method according to claim 11 wherein saidprogrammable unit includes a data shifting network coupled to saiddecoder, and wherein:the first storing step includes the storing of afirst set of signals which, when fetched from said second memory,effects a shift of said data shifting network; and the second storingstep includes the storing of a second set of signals which containssignals to establish the number of bit positions by which said data isto be shifted.